[jbossts-issues] [JBoss JIRA] (JBTM-867) Create an ultra high performance distributed transaction coordinator to handle infinispan, JMS, websevice(with compensation logic), file system resources and database transactions.

Tom Jenkinson (JIRA) jira-events at lists.jboss.org
Mon Oct 14 07:49:36 EDT 2013


     [ https://issues.jboss.org/browse/JBTM-867?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel ]

Tom Jenkinson updated JBTM-867:
-------------------------------

    Fix Version/s:     (was: 4.17.0)

    
> Create an ultra high performance distributed transaction coordinator to handle infinispan, JMS, websevice(with compensation logic), file system resources and database transactions.
> ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
>
>                 Key: JBTM-867
>                 URL: https://issues.jboss.org/browse/JBTM-867
>             Project: JBoss Transaction Manager
>          Issue Type: Feature Request
>      Security Level: Public(Everyone can see) 
>          Components: JTS
>            Reporter: Magnus Magnus
>            Assignee: Tom Jenkinson
>
> Create an ultra high performance distributed transaction coordinator to handle infinispan, JMS, websevice(with compensation logic), file system resources and database transactions. Current XA implementations cause high performace degradation.
> Transaction logs should be stored in massively parallelized sql/file backing stores(Use an infinispan write through cache region to store tx logs?) on the nodes.
> Transaction manager should be able to work only with a webcontainer lie Tomcat (without a real application server).
> Transaction coordinator should use blocking free(As much as possible. Use profiler like JProfiler or others heavily to detect locking/blocking issues) architecture in the source code to allow ultra high transaction counts (thousands/sec per server). It is necessary for new distributed cache architectures. 

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