[jboss-jira] [JBoss JIRA] (WFLY-1702) Investigate module wiring consistency at build time

Tue Jul 16 07:11:26 EDT 2013

    [ https://issues.jboss.org/browse/WFLY-1702?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel&focusedCommentId=12789882#comment-12789882 ] 

Thomas Diesler edited comment on WFLY-1702 at 7/16/13 7:09 AM:
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I suggest we bring the pull request in as is (i.e. without failing the build) and work with the respective folks to white list the false errors. When errors are down to zero we can switch to failOnError=true to prevent future errors.

      was (Author: thomas.diesler):
    I suggest we bring the pull request in as is and work with the respective folks to white list the false errors. When errors are down to zero we can switch to failOnError=true to prevent future errors.

> Investigate module wiring consistency at build time
> ---------------------------------------------------
>
>                 Key: WFLY-1702
>                 URL: https://issues.jboss.org/browse/WFLY-1702
>             Project: WildFly
>          Issue Type: Task
>          Components: Build System
>            Reporter: Thomas Diesler
>            Assignee: Thomas Diesler
>             Fix For: 8.0.0.Alpha3
>
>
> Due to the use of human wiring decisions it is possible that the initial modules wiring setup is incomplete/inconsistent. Various inconsistencies can occur 
> * There are code paths in a module that require a class load for which there is no dependency defined
> * Modules define (stale) dependencies that are never used
> * Modules define dependencies that are inconsistent in the class space

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