1PC can cause a window of inconsistency with L1 invalidation ------------------------------------------------------------ Key: ISPN-3518 URL: https://issues.jboss.org/browse/ISPN-3518 Project: Infinispan Issue Type: Bug Components: Distributed Cache Affects Versions: 5.3.0.Final Reporter: William Burns Assignee: William Burns Labels: jdg620_dm, jdg62GAblocker The L1TxInterceptor currently doesn't block on L1 invalidations during a 1PC. This can cause an inconsistent view of data across non owner nodes. Example: {quote} Node A owns k with value of v1 Node B has k in L1 with value of v1 tx1 started Node A put k -> v2 Node A sends invalidation Node A commits tx1 completed tx2 started Node B get k returns v1 from L1 tx2 completed Node B gets invalidation for k tx3 started Node B get k remotely retrieves v2 from Node A tx3 completed {quote} We need to make sure that all L1 invalidations in Tx mode are completed before completing the transaction.